1. Field of the Invention
This invention relates to computer systems, and more particularly to computer systems providing clock signals to synchronous memory devices.
2. Description of the Related Art
A typical computer system uses several different clock signals to synchronize system operations. Clock signals periodically transition between a low voltage level and a high voltage level, and system operations are cued to these transitions. System clock signals may include, for example, a processor clock signal, a system bus clock signal, an expansion (e.g., peripheral component interconnect or PCI) bus clock signal, and a floppy disk clock signal. A single clock generator typically generates all of the various system clock signals.
The clock signals are typically distributed to system components via various signal lines and buffers. The clock signals propagate along the signal lines at finite velocities, incurring time delays dependent upon the lengths of the various signal lines. Propagation delays of the buffers add to the propagation delays of the signal lines, resulting in xe2x80x9cclock skew.xe2x80x9d Clock skew is the difference in time between transitions of a clock signal at the different locations of receiving components throughout the computer system.
The typical computer system includes a processor coupled to a memory unit. During operation, the processor stores data within, and retrieves data from, the memory unit. The memory unit may include synchronous dynamic random access memory (SDRAM) devices which synchronize all inputs and outputs to the processor clock signal. SDRAM devices store or xe2x80x9clatchxe2x80x9d incoming memory access signals in response to the processor clock signal. After the incoming memory access signals have been latched, the processor is free to handle other tasks. Following the latching of memory access signals relaying a read request, data stored within SDRAM devices is made available to the processor at output pins after a specific number of cycles of the processor clock signal. SDRAM devices also offer a number of other features which may be employed to improve the performance of the computer system, including burst mode data transfer capability.
Clock skew between the processor and a memory unit including SDRAM devices must be accounted for, and represents a period of time immediately following a transition of the processor clock signal during which no useful memory access task can be performed. As the frequency of the processor clock signal increases, the fraction of the processor clock cycle which cannot be used due to clock skew increases. In order to retain the capability to provide data to the processor in a single processor clock cycle, the speed of circuitry within the memory unit may have to be increased with any increase in processor clock signal frequency. Such faster memory devices tend to be more expensive, increasing computer system manufacturing costs.
It would thus be desirable to have a computer system employing a clock signal distribution system which reduces clock skew between the processor and a memory unit including synchronous memory devices. Such a clock signal distribution system would allow the frequency of the processor clock signal, and the performance of the computer system, to be increased without requiring faster and more expensive memory devices.
A computer system is described including a processor for executing instructions, a memory module for storing instructions and data, and a memory controller coupled between the processor and the memory module. The memory controller provides a differential clock signal and memory access signals which are routed to the memory module. The memory module includes multiple memory devices coupled to a clock buffer. The clock buffer produces a new single-ended xe2x80x9cregeneratedxe2x80x9d clock signal from the differential clock signal. The clock buffer includes an input buffer circuit and a phase-locked loop (PLL). The input buffer circuit receives the differential clock signal from the memory controller and produces a single-ended reference clock signal from the differential clock signal. The PLL produces the single-ended regenerated clock signal substantially at the same frequency of, and in synchronization with, the single-ended reference clock signal produced by the input buffer circuit.
Each of the multiple memory devices is coupled to receive the regenerated clock signal, and the operations of the multiple memory devices are synchronized to the regenerated clock signal. The multiple memory devices within the memory module may also be coupled to receive the memory access signals produced by the memory controller, and may store data or retrieve data in response to the memory access signals and the regenerated clock signal. The multiple memory devices may include synchronous dynamic random access memory (SDRAM) devices, and the memory module may be a dual in-line memory module (DIMM).
The differential clock signal may include a pair of complementary low voltage positive emitter-coupled logic (LVPECL) signals. As defined herein, LVPECL signals are generated by emitter-coupled logic (ECL) circuits operated in positive ECL (PECL) mode using a positive power supply voltage level of less than +5.0 volts referenced to a ground power supply potential. For example, the pair of complementary LVPECL signals of the differential clock signal may be generated using a power supply voltage of +3.3 volts, and may alternate periodically between a logic high voltage level of about +2.4 volts and a logic low voltage level of approximately +1.6 volts.
The input buffer circuit may include level translation circuitry for converting the single-ended reference clock signal from a LVPECL signal to a low voltage transistor-transistor logic (LVTTL) signal. That is, the level translation circuitry may shift the logic high and logic low voltage levels of the single-ended reference clock signal from the LVPECL levels of the differential clock signal to logic high and logic low voltage levels of LVTTL signals. Following conversion from a LVPECL signal to a LVTTL signal, the single-ended reference clock signal may alternate periodically between a logic high voltage level of greater than or equal to about +2.0 volts and a logic low voltage level of less than or equal to approximately +0.8 volts.
The computer system may include n memory modules, nxe2x89xa71, and each memory module may include multiple memory devices coupled to a clock buffer. The memory controller may be coupled to the processor and to each of the n memory modules. The computer system may also include a fanout buffer coupled to the memory controller and to each of the n memory modules. The memory controller may provide the differential clock signal to the fanout buffer. The fanout buffer may produce n copies of the differential clock signal, and may provide a different copy of the differential clock signal to each of the n memory modules. Each clock buffer within a given memory module may produce the single-ended regenerated clock signal as described above and provide the regenerated clock signal to the multiple memory devices within the memory module.
The fanout buffer may include multiple buffer circuits with differential inputs and differential outputs. The buffer circuits may include ECL circuits operated in PECL mode as described above. Each buffer circuit may include a differential amplifier input section and an emitter follower output section. The fanout buffer may be coupled to the memory controller and to each of the n memory modules by a different pair of signal lines having selected electrical impedances and propagation delays.
The PLL of each clock buffer may include a phase comparator, a loop filter, and a voltage-controlled oscillator (VCO) connected in series. An output of the VCO may be coupled to inputs of multiple output buffer circuits producing the regenerated clock signal. The phase comparator may have two inputs, and the reference clock signal produced by the input buffer circuit may be applied to one of the inputs of the phase comparator. An output of one of the output buffer circuits may be fed back to the other input of the phase comparator. As a result, the single-ended regenerated clock signal produced at the outputs of the output buffer circuits is substantially at the same frequency of, and in synchronization with, the single-ended reference clock signal produced by the input buffer circuit.